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National Taiwan University Will Present Our Academic Achievement at 2012 ISCC with Four Accepted Articles

The College of Electrical Engineering and Computer Science of National Taiwan University has just received another great honor in the academic field! There are four research papers accepted by the ISCC (International Solid-State Circuits Conference), instructed by the following professors in the Graduate Institute of Electronic Engineering: Professor Chen Liang-Gee, Professor Wang Chrong-Kuang, Professor Liu Shen-Luan, and Professor Chen Chung-Ping. ISSCC is the flagship conference of the Solid-State Circuits Society, and is the premier forum for the presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity to network with leading experts in the field. The four research papers from National Taiwan University are the half of the accepted articles from Taiwan. This academic performance marks that National Taiwan University has made us the top research team in the field of IC design. Also, our R&D and innovative design of its techniques have been improved and way beyond the others.

IEEE SSCS (IEEE Solid-State Circuits Society) has been holding ISSCC (International Solid-State Circuits Conference) ever since 1953. This conference is one significant indication of global development of advanced solid-state circuits semiconductor industries. Very few articles can be accepted by ISSCC, the top academic recognition in the filed of IC development.

Professor Chen Liang-Gee’s Topic of the Accepted Article: Neocortical Computing System-on-Chip

DSPIC Lab, the IC design lab, organized and led by Professor Chen Liang-Gee developed the Computing System-on-Chip to imitate the structure and the network layer of cerebral cortex development, the neural patterns, and the structure of neural visual network. Chen Liang-Gee and the DSPIC group members developed the chip with the identification features same as the human brains. The Neocortical Computing System-on-Chip does not rely on the conventional computing system; instead, it combines the practice of neuroscience and thus turned neuroscience into the same concept as the IC design. This neocortical computing features the accessible abilities of self-maintaining, self-organizing, and self-healing. For ISSCC, the topic in this article is the first accepted research paper combined with neuroscience. Practically speaking, the Neocortical Computing System-on-Chip can be definitely put into practice for the identification of objects, including people, animals, locations and the actions. Hopefully, it will soon be applied to the auto-driving, robots’ vision, and security monitors.

Professor Wang Chrong-Kuang’s Topic of the Accepted Article: The Efficient Power Amplifier

In the front-end of wireless data transmission, PA (power amplifier) affects the transmission of certain signals and consumes one- third energy in the process. Therefore, the efficiency of the power amplifier plays a crucial role. With Professor Wang Chrong-Kuang’s instruction, Wang Kun-Yin of the VLSI (very-large-scale integration) Circuits and Systems Lab has developed the power amplifier with great efficiency, which can be applied to the vehicular radar systems within 60-90 GHz and the wireless P2P (point-to-point) broadband network. Under the condition of consuming the same energy, this efficient power amplifier can increase a doubled output power instead of the conventional way. The postgraduate student from the Graduate Institute of Electronic Engineering, Wang Kun-Yin, has made the innovative power combiner a great breakthrough in comparison to the miss-match of the traditional ones. This will definitely benefit the vehicular radar system and the wireless network among buildings with a better efficiency.

Professor Chen Chung-Ping’s Topic of the Accepted Article: The Broadband All-Digital DLL (Delay-Locked Loop) Chip

Hsieh Min-Han and Chen Liang-Hsin of the Graduate Institute of Electronic Engineering designed The Broadband All-Digital DLL (Delay-Locked Loop) Chip with the instruction of Professor Chen Chung-Ping and Professor Liu Shen-Luan. The delay-locked loop provides the clock signal and makes sure the signal can be processed synchronously. Therefore, the transmission between chips can thus provide correct information via synchronous process. This helps a lot maintaining the correct information of any particular electrical device. Hsieh Min-Han, the Ph. D. student of the Graduate Institute of Electronic Engineering, confirms that the Broadband All-Digital Delay-Locked Loop Chip based on phase-tracing unit is a great substitute of the delay-line constituted of many delay units. Their chip is compatible to systems of different commanders; also, it reduces much more consumed power than the conventional products do while processing, which is energy saving and efficient. Besides, the system on chips is more solid and stable than the traditional loop, and it can be easily intergrated. Thus, through this method and in comparison to the other products, the Broadband All-Digital Delay-Locked Loop Chip can be designed along with the chips of CPU, DRAM, and GPU. Also, it consumes less power while processing and makes each chip connected in a small scale.

Professor Liu Shen-Luan’s Topic of the Accepted Article: 2.4 GHz Low Noise PLL (Phase-Locked Loop)

A phase-locked loop or phase lock loop (PLL) is an electronic circuit consisting of a variable frequency oscillator and a phase detector. PLL is a control system that generates an output signal whose phase is related to the phase of an input reference signal. Phase-locked loops can be used to recover a signal from a noisy communication channel, generate stable frequencies at a multiple of an input frequency, or distribute clock-timing pulses in digital logic designs such as microprocessors. As for the low noise phase-locked loop, this can be used to process the clock generator and digital adaptors. Through the technique of sub-harmonically injection lock, the low noise PLL can reduce the noise of the oscillator. The conventional technique of PLL is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz. Professor Liu Shen-Luan and the post-graduate student, Huang Yi-Jie, of the Graduate Institute of Electronic Engineering indicate an innovative technique to improve the clock-timing pulses to make the system of sub-harmonically locked loop stable.

The 2012 ISSCC is going to be held in San Francisco during February 19th and February 23rd. There will be nine research papers from Taiwan presented at the conference, which is indeed a great honor. In addition to the four articles from National Taiwan University, there are also two research papers accepted each from National Tsing Hua University and MediaTek, and one article accepted from National Chiao Tung University. Hence, National Taiwan University will have the opportunity to present our outstanding academic performance to the whole world.

Chinese version